Forum Linux.embarqué Port ethernet up mais aucun flux

• # Adresse ?

  Posté par AncalagonTotof le 21 avril 2023 à 21:39. Évalué à 2.

  

  [nb: si le message est encore éditable, il faut passer une ligne avant les premiers ```, pas après]

  Est-ce que l'interface réseau a obtenu une adresse par DHCP ou bien possède une IP fixe ?
  (ifconfig ou ip addr pour vérifier).

  Peut-être alors un problème de route ? (route -n et je ne sais plus exactement avec ip)

  • [^] # Re: Adresse ?

    Posté par doudootiana le 21 avril 2023 à 22:32. Évalué à 1.

    

    Hello.
    tout d'abord, merci pour ta réponse :)

    J'ai oublié de dire que je n'arrive pas à avoir d'adresse IP pour l'interface eth2 en dhcp.

    J'ai également essayé en ip statique.
    Impossible de pinguer la passerelle.

    J'ai testé le câble sur les autres ports, et j'ai quand même essayé avec un autre cable rj45.
    Ca n'a rien changé:(

• # ethtool et vérification câble

  Posté par Yves Bourguignon le 21 avril 2023 à 21:48. Évalué à 3.

  

  2 commandes d'aide au diagnostic :
  sudo ethtool -t eth2 (exécute un autotest de l'interface)
  sudo ethtool -S eth2 (interroge les statistiques de l'interface en Tx et Rx)

  Et vérification hardware :
  Échange les câbles entre celui sur eth1 (qui fonctionne c'est sûr) et celui sur eth2.
  Change de port sur le switch.

  • [^] # Re: ethtool et vérification câble

    Posté par doudootiana le 21 avril 2023 à 22:35. Évalué à 1.

    

    Hello.
    Merci pour ta réponse.

    La commande ethtool -S sort tout à zéro.

    et pour la commande ethtool -t

    # ethtool -t eth2
    Cannot test: Operation not supported
    

    Côté hardware :
    j'ai testé le câble sur les autres ports.
    J'ai également essayé avec un autre câble rj45. :(

    • [^] # Re: ethtool et vérification câble

      Posté par Yves Bourguignon le 22 avril 2023 à 10:56. Évalué à 3.

      

      # ethtool -t eth2
Cannot test: Operation not supported

      Le "-t" lance un autotest mais ne peut pas le faire en cours d'utilisation (je crois).
      - Débranche le câble de ce port eth2 avant de lancer la commande d'autotest.
      - Enlève le "-t" pour voir si elle répond avec son status : $ sudo ethtool eth2 (avec et sans le câble).
      - Essaye plusieurs paramètres comme : $ sudo ethtool -s eth2 autoneg off pour voir comment elle réagit.
      - man ethtool

• # DTB ?

  Posté par Cyril Brulebois (site web personnel) le 22 avril 2023 à 20:57. Évalué à 3.

  

  Hello,

  Il y a une chose que je trouve surprenante, c'est qu'il y a apparemment une symétrie sur eth1/eth2, au moins en terme de module utilisé (Marvell 88E1510), et je m'attendrais à avoir les mêmes caractéristiques. En revanche, la configuration se fait en inband/sgmii pour eth1 tandis qu'elle se fait en phy/rgmii-id pour eth2 (cf. MII pour les détails).

  Si je regarde arch/arm64/boot/dts/marvell/cn9130-db.dtsi dans le code source du noyau Linux, je vois des choses cohérentes par rapport aux spécifications constructeur :

  2 x Ethernet RJ45 10/100/1000
  1 x SFP+ 10GbE
  

  à savoir (je conserve uniquement le plus pertinent) :

  /* SLM-1521-V2, CON9 */
  &cp0_eth0 {
          phy-mode = "10gbase-r";
          managed = "in-band-status";
  };
  
  /* CON56 */
  &cp0_eth1 {
          phy-mode = "rgmii-id";
  };
  
  /* CON57 */
  &cp0_eth2 {
          phy-mode = "rgmii-id";
  };
  

  Cela dit, il y a beaucoup de variantes cn913* !

  Il serait bon de savoir quelles sont les caractéristiques exactes de ta machine, quelle est la version exacte du noyau, quelle DTB est utilisée, et si c'est effectivement la bonne.

  En tout cas, c'est par là que je commencerais.

  (Pourquoi je suggère cela : j'ai déjà vu des Pi CM3 se prendre pour des Pi 3 — ça ne marche pas du tout — et des Pi CM4 se prendre pour des Pi 4B — c'est pire, ça marche presque, sauf qu'il manque des morceaux — parce que le chargeur de démarrage se prenait les pieds dans le tapis et n'utilisait pas la bonne DTB.)

  Debian Consultant @ DEBAMAX

  • [^] # Re: DTB ?

    Posté par doudootiana le 22 avril 2023 à 23:07. Évalué à 1. Dernière modification le 22 avril 2023 à 23:07.

    

    Sommaire

    • include "cn9130.dtsi"
    • include
    • include
    • include "cn9130.dtsi"
    • include
    • include
    • include "cn9130.dtsi"
    • include
    • include

    Hello
    Je te remercie pour ta réponse.

    Ton avis est très intéressant, je vais travailler dessus.

    Je possède une clearfog base cn9130.
    J'utilise le kernel 6.2
    Le dts n'est pas natif dans le kernel, je l'ai édité à l'aide des patchs du constructeur :
    ```
    // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    /*
    * Copyright SolidRun Ltd.
    *
    * Device tree for the CN9130 based SOM.
    */

    include "cn9130.dtsi"

    include

    include

    / {
    model = "SolidRun CN9130 based SOM Clearfog Base";

    chosen {
        stdout-path = "serial0:115200n8";
    };
    
    aliases {
        gpio1 = &cp0_gpio1;
        gpio2 = &cp0_gpio2;
        i2c0 = &cp0_i2c0;
        ethernet0 = &cp0_eth0;
        ethernet1 = &cp0_eth1;
        ethernet2 = &cp0_eth2;
        spi1 = &cp0_spi0;
        spi2 = &cp0_spi1;
    };
    
    memory@00000000 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>;
    };
    v_3_3: regulator-3-3v {
        compatible = "regulator-fixed";
        regulator-name = "v_3_3";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
        status = "okay";
    };
    ap0_reg_sd_vccq: ap0_sd_vccq@0 {
        compatible = "regulator-gpio";
        regulator-name = "ap0_sd_vccq";
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
        states = <1800000 0x1 3300000 0x0>;
    };
    
    cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
        compatible = "regulator-fixed";
        regulator-name = "cp0-xhci0-vbus";
        regulator-min-microvolt = <5000000>;
        regulator-max-microvolt = <5000000>;
        enable-active-high;
    };
    
    cp0_usb3_0_phy0: cp0_usb3_phy@0 {
        compatible = "usb-nop-xceiv";
        vcc-supply = <&cp0_reg_usb3_vbus0>;
    };
    
    cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
        compatible = "regulator-fixed";
        regulator-name = "cp0-xhci1-vbus";
        regulator-min-microvolt = <5000000>;
        regulator-max-microvolt = <5000000>;
        enable-active-high;
    };
    
    cp0_usb3_0_phy1: cp0_usb3_phy@1 {
        compatible = "usb-nop-xceiv";
        vcc-supply = <&cp0_reg_usb3_vbus1>;
    };
    
    cp0_reg_sd_vccq: cp0_sd_vccq@0 {
        compatible = "regulator-gpio";
        regulator-name = "cp0_sd_vccq";
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <3300000>;
        states = <1800000 0x1
            3300000 0x0>;
    };
    
    cp0_reg_sd_vcc: cp0_sd_vcc@0 {
        compatible = "regulator-fixed";
        regulator-name = "cp0_sd_vcc";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        enable-active-high;
        regulator-always-on;
    };
    
    cp0_sfp_eth0: sfp-eth@0 {
        compatible = "sff,sfp";
        i2c-bus = <&cp0_i2c1>;
        los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
        mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
        tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
        tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
        maximum-power-milliwatt = <2000>;
    };
    
    keys {
                compatible = "gpio-keys";
                pinctrl-0 = <&cp0_button_pin>;
                pinctrl-names = "default";
    
        button0{
            /* SW3 button */
            label = "SW3";
            gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
            linux,can-disable;
            linux,code = <BTN_0>;
        };
    };
    

    };

    &uart0 {
    status = "okay";
    };

    /* on-board eMMC */
    &ap_sdhci0 {
    pinctrl-names = "default";
    bus-width = ;
    vqmmc-supply = <&ap0_reg_sd_vccq>;
    status = "okay";
    };

    &cp0_crypto {
    status = "disabled";
    };

    &cp0_ethernet {
    status = "okay";
    };

    &cp0_gpio1 {
    status = "okay";
    };

    &cp0_gpio2 {
    status = "okay";
    };

    /* EEPROM */
    &cp0_i2c0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c0_pins>;
    clock-frequency = ;

    /*
     * PCA9655 GPIO expander, up to 1MHz clock.
     *  0-CON3 CLKREQ#
     *  1-CON3 PERST#
     *  2-M2 FUL_CARD_POWER_OFF
     *  3-CON3 W_DISABLE
     *  4-CON2 CLKREQ#
     *  5-USB3 overcurrent
     *  6-USB3 power
     *  7-CON2 W_DISABLE
     *  8-M2 W_DISABLE
     *  9-JP4 P4
     * 10-M2 RESET
     * 11-m.2 DEVSLP
     * 12-SFP_LOS
     * 13-SFP_TX_FAULT
     * 14-SFP_TX_DISABLE
     * 15-SFP_MOD_DEF0
     */
    expander0: gpio-expander@20 {
        /*
         * This is how it should be:
         * compatible = "onnn,pca9655", "nxp,pca9555";
         * but you can't do this because of the way I2C works.
         */
        compatible = "nxp,pca9555";
        gpio-controller;
        #gpio-cells = <2>;
        reg = <0x20>;
    
        pcie1_0_clkreq {
            gpio-hog;
            gpios = <0 GPIO_ACTIVE_LOW>;
            input;
            line-name = "pcie1.0-clkreq";
        };
        m2_ful_card_power_off {
            gpio-hog;
            gpios = <2 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "m2-ful-card-power-off";
        };
        pcie1_0_w_disable {
            gpio-hog;
            gpios = <3 GPIO_ACTIVE_LOW>;
            output-low;
            line-name = "pcie1.0-w-disable";
        };
        usb3_ilimit {
            gpio-hog;
            gpios = <5 GPIO_ACTIVE_LOW>;
            input;
            line-name = "usb3-current-limit";
        };
        usb3_power {
            gpio-hog;
            gpios = <6 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "usb3-power";
        };
        m2_w_disable {
            gpio-hog;
            gpios = <8 GPIO_ACTIVE_LOW>;
            output-low;
            line-name = "m2-w-disable";
        };
        m2_reset {
            gpio-hog;
            gpios = <10 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "m2-reset";
        };
        m2_devslp {
            gpio-hog;
            gpios = <11 GPIO_ACTIVE_HIGH>;
            output-low;
            line-name = "m.2 devslp";
        };
    };
    
    /* The MCP3021 supports standard and fast modes */
    mikrobus_adc: mcp3021@4c {
        compatible = "microchip,mcp3021";
        reg = <0x4c>;
    };
    
    /*EEPROM on the SOM */
    eeprom@53 {
        compatible = "atmel,24c02";
        reg = <0x53>;
        pagesize = <16>;
    };
    

    };

    /* I2C Master */
    &cp0_i2c1 {
    status = "okay";
    clock-frequency = ;
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c1_pins>;
    };

    &cp0_gpio1 {
    phy_reset { /* Release switch reset */
    gpio-hog;
    gpios = ;
    output-high;
    };
    };

    &cp0_mdio {
    status = "okay";
    phy0: ethernet-phy@0 {
    /* Green led blinks on activity, Orange LED on link /
    marvell,reg-init = ;
    reg = ;
    };
    phy1: ethernet-phy@1 {
    / Green led blinks on activity, Orange LED on link */
    marvell,reg-init = ;
    reg = ;
    };
    };

    /* SRDS #0 - SATA on M.2 connector */
    &cp0_sata0 {
    status = "okay";
    };

    /* SRDS #1 - USB 3.0 host */
    &cp0_usb3_0 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy0>;
    phy-names = "usb";
    };

    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    };

    /* SRDS #2 - SFP+ 10GE */
    &cp0_eth0 {
    status = "okay";
    phy-mode = "10gbase-r";
    local-mac-address = [64 69 61 67 62 03];
    phys = <&cp0_comphy2 0>;
    managed = "in-band-status";
    sfp = <&cp0_sfp_eth0>;
    };

    /* SRDS #3 - SGMII 1GE on carrier board */
    &cp0_eth1 {
    status = "okay";
    local-mac-address = [64 69 61 67 62 01];
    phys = <&cp0_comphy3 1>;
    phy = <&phy1>;
    managed = "in-band-status";
    phy-mode = "sgmii";
    };

    /* SRDS #4 - USB 3.0 host on M.2 connector */
    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    phy-names = "usb";
    };

    /* SRDS #5 - mini PCIe slot */
    &cp0_pcie2 {
    status = "okay";
    phys = <&cp0_comphy5 2>;
    num-lanes = ;
    reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
    };

    /* GE PHY RGMII /
    &cp0// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    /
    * Copyright SolidRun Ltd.
    *
    * Device tree for the CN9130 based SOM.
    */

    include "cn9130.dtsi"

    include

    include

    / {
    model = "SolidRun CN9130 based SOM Clearfog Base";

    chosen {
        stdout-path = "serial0:115200n8";
    };
    
    aliases {
        gpio1 = &cp0_gpio1;
        gpio2 = &cp0_gpio2;
        i2c0 = &cp0_i2c0;
        ethern// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    

    /*
    * Copyright SolidRun Ltd.
    *
    * Device tree for the CN9130 based SOM.
    */

    include "cn9130.dtsi"

    include

    include

    / {
    model = "SolidRun CN9130 based SOM Clearfog Base";

    chosen {
        stdout-path = "serial0:115200n8";
    };
    
    aliases {
        gpio1 = &cp0_gpio1;
        gpio2 = &cp0_gpio2;
        i2c0 = &cp0_i2c0;
        ethernet0 = &cp0_eth0;
        ethernet1 = &cp0_eth1;
        ethernet2 = &cp0_eth2;
        spi1 = &cp0_spi0;
        spi2 = &cp0_spi1;
    };
    
    memory@00000000 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>;
    };
    v_3_3: regulator-3-3v {
        compatible = "regulator-fixed";
        regulator-name = "v_3_3";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
        status = "okay";
    };
    ap0_reg_sd_vccq: ap0_sd_vccq@0 {
        compatible = "regulator-gpio";
        regulator-name = "ap0_sd_vccq";
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
        states = <1800000 0x1 3300000 0x0>;
    };
    
    cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
        compatible = "regulator-fixed";
        regulator-name = "cp0-xhci0-vbus";
        regulator-min-microvolt = <5000000>;
        regulator-max-microvolt = <5000000>;
        enable-active-high;
    };
    
    cp0_usb3_0_phy0: cp0_usb3_phy@0 {
        compatible = "usb-nop-xceiv";
        vcc-supply = <&cp0_reg_usb3_vbus0>;
    };
    
    cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
        compatible = "regulator-fixed";
        regulator-name = "cp0-xhci1-vbus";
        regulator-min-microvolt = <5000000>;
        regulator-max-microvolt = <5000000>;
        enable-active-high;
    };
    
    cp0_usb3_0_phy1: cp0_usb3_phy@1 {
        compatible = "usb-nop-xceiv";
        vcc-supply = <&cp0_reg_usb3_vbus1>;
    };
    
    cp0_reg_sd_vccq: cp0_sd_vccq@0 {
        compatible = "regulator-gpio";
        regulator-name = "cp0_sd_vccq";
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <3300000>;
        states = <1800000 0x1
            3300000 0x0>;
    };
    
    cp0_reg_sd_vcc: cp0_sd_vcc@0 {
        compatible = "regulator-fixed";
        regulator-name = "cp0_sd_vcc";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        enable-active-high;
        regulator-always-on;
    };
    
    cp0_sfp_eth0: sfp-eth@0 {
        compatible = "sff,sfp";
        i2c-bus = <&cp0_i2c1>;
        los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
        mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
        tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
        tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
        maximum-power-milliwatt = <2000>;
    };
    
    keys {
                compatible = "gpio-keys";
                pinctrl-0 = <&cp0_button_pin>;
                pinctrl-names = "default";
    
        button0{
            /* SW3 button */
            label = "SW3";
            gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
            linux,can-disable;
            linux,code = <BTN_0>;
        };
    };
    

    };

    &uart0 {
    status = "okay";
    };

    /* on-board eMMC */
    &ap_sdhci0 {
    pinctrl-names = "default";
    bus-width = ;
    vqmmc-supply = <&ap0_reg_sd_vccq>;
    status = "okay";
    };

    &cp0_crypto {
    status = "disabled";
    };

    &cp0_ethernet {
    status = "okay";
    };

    &cp0_gpio1 {
    status = "okay";
    };

    &cp0_gpio2 {
    status = "okay";
    };

    /* EEPROM */
    &cp0_i2c0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c0_pins>;
    clock-frequency = ;

    /*
     * PCA9655 GPIO expander, up to 1MHz clock.
     *  0-CON3 CLKREQ#
     *  1-CON3 PERST#
     *  2-M2 FUL_CARD_POWER_OFF
     *  3-CON3 W_DISABLE
     *  4-CON2 CLKREQ#
     *  5-USB3 overcurrent
     *  6-USB3 power
     *  7-CON2 W_DISABLE
     *  8-M2 W_DISABLE
     *  9-JP4 P4
     * 10-M2 RESET
     * 11-m.2 DEVSLP
     * 12-SFP_LOS
     * 13-SFP_TX_FAULT
     * 14-SFP_TX_DISABLE
     * 15-SFP_MOD_DEF0
     */
    expander0: gpio-expander@20 {
        /*
         * This is how it should be:
         * compatible = "onnn,pca9655", "nxp,pca9555";
         * but you can't do this because of the way I2C works.
         */
        compatible = "nxp,pca9555";
        gpio-controller;
        #gpio-cells = <2>;
        reg = <0x20>;
    
        pcie1_0_clkreq {
            gpio-hog;
            gpios = <0 GPIO_ACTIVE_LOW>;
            input;
            line-name = "pcie1.0-clkreq";
        };
        m2_ful_card_power_off {
            gpio-hog;
            gpios = <2 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "m2-ful-card-power-off";
        };
        pcie1_0_w_disable {
            gpio-hog;
            gpios = <3 GPIO_ACTIVE_LOW>;
            output-low;
            line-name = "pcie1.0-w-disable";
        };
        usb3_ilimit {
            gpio-hog;
            gpios = <5 GPIO_ACTIVE_LOW>;
            input;
            line-name = "usb3-current-limit";
        };
        usb3_power {
            gpio-hog;
            gpios = <6 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "usb3-power";
        };
        m2_w_disable {
            gpio-hog;
            gpios = <8 GPIO_ACTIVE_LOW>;
            output-low;
            line-name = "m2-w-disable";
        };
        m2_reset {
            gpio-hog;
            gpios = <10 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "m2-reset";
        };
        m2_devslp {
            gpio-hog;
            gpios = <11 GPIO_ACTIVE_HIGH>;
            output-low;
            line-name = "m.2 devslp";
        };
    };
    
    /* The MCP3021 supports standard and fast modes */
    mikrobus_adc: mcp3021@4c {
        compatible = "microchip,mcp3021";
        reg = <0x4c>;
    };
    
    /*EEPROM on the SOM */
    eeprom@53 {
        compatible = "atmel,24c02";
        reg = <0x53>;
        pagesize = <16>;
    };
    

    };

    /* I2C Master */
    &cp0_i2c1 {
    status = "okay";
    clock-frequency = ;
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c1_pins>;
    };

    &cp0_gpio1 {
    phy_reset { /* Release switch reset */
    gpio-hog;
    gpios = ;
    output-high;
    };
    };

    &cp0_mdio {
    status = "okay";
    phy0: ethernet-phy@0 {
    /* Green led blinks on activity, Orange LED on link /
    marvell,reg-init = ;
    reg = ;
    };
    phy1: ethernet-phy@1 {
    / Green led blinks on activity, Orange LED on link */
    marvell,reg-init = ;
    reg = ;
    };
    };

    /* SRDS #0 - SATA on M.2 connector */
    &cp0_sata0 {
    status = "okay";
    };

    /* SRDS #1 - USB 3.0 host */
    &cp0_usb3_0 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy0>;
    phy-names = "usb";
    };

    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    };

    /* SRDS #2 - SFP+ 10GE */
    &cp0_eth0 {
    status = "okay";
    phy-mode = "10gbase-r";
    local-mac-address = [64 69 61 67 62 03];
    phys = <&cp0_comphy2 0>;
    managed = "in-band-status";
    sfp = <&cp0_sfp_eth0>;
    };

    /* SRDS #3 - SGMII 1GE on carrier board */
    &cp0_eth1 {
    status = "okay";
    local-mac-address = [64 69 61 67 62 01];
    phys = <&cp0_comphy3 1>;
    phy = <&phy1>;
    managed = "in-band-status";
    phy-mode = "sgmii";
    };

    /* SRDS #4 - USB 3.0 host on M.2 connector */
    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    phy-names = "usb";
    };

    /* SRDS #5 - mini PCIe slot */
    &cp0_pcie2 {
    status = "okay";
    phys = <&cp0_comphy5 2>;
    num-lanes = ;
    reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
    };

    /* GE PHY RGMII */
    &cp0_eth2 {
    status = "okay";
    local-mac-address = [64 69 61 67 62 02];
    phy = <&phy0>;
    phy-mode = "rgmii-id";
    pinctrl-0 = <&cp0_ge2_rgmii_pins>;
    };

    &cp0_sdhci0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_sdhci_pins
    &cp0_sdhci_cd_pins>;
    bus-width = ;
    cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
    no-1-8-v;
    vqmmc-supply = <&v_3_3>;
    vmmc-supply = <&v_3_3>;
    };

    &cp0_spi1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_spi1_pins>;
    reg = ;
    spi-flash@0 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    spi-max-frequency = ;
    };
    spi-flash@1 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    /* On carrier MUX does not allow higher frequencies */
    spi-max-frequency = ;
    };
    };

    &cp0_syscon0 {
    cp0_pinctrl: pinctrl {
    compatible = "marvell,cp115-standalone-pinctrl";
    cp0_i2c0_pins: cp0-i2c-pins-0 {
    marvell,pins = "mpp37", "mpp38";
    marvell,function = "i2c0";
    };
    cp0_i2c1_pins: cp0-i2c-pins-1 {
    marvell,pins = "mpp35", "mpp36";
    marvell,function = "i2c1";
    };
    cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-0 {
    marvell,pins = "mpp44", "mpp45", "mpp46",
    "mpp47", "mpp48", "mpp49",
    "mpp50", "mpp51", "mpp52",
    "mpp53", "mpp54", "mpp55";
    marvell,function = "ge1";
    };
    cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
    marvell,pins = "mpp43";
    marvell,function = "sdio";
    };
    cp0_sdhci_pins: cp0-sdhi-pins-0 {
    marvell,pins = "mpp56", "mpp57", "mpp58",
    "mpp59", "mpp60", "mpp61";
    marvell,function = "sdio";
    };
    cp0_spi1_pins: cp0-spi-pins-1 {
    marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
    marvell,function = "spi1";
    };
    /* cp0_rcvr_clk_pins: cp0-rcvr-clk-pins {
    marvell, pins = "mpp40";
    marvell,function = "synce1";
    };*/
    cp0_button_pin: cp0-button-pin {
    marvell,pins = "mpp32";
    marvell,function = "gpio";
    };
    };
    };
    et0 = &cp0_eth0;
    ethernet1 = &cp0_eth1;
    ethernet2 = &cp0_eth2;
    spi1 = &cp0_spi0;
    spi2 = &cp0_spi1;
    };
    memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
v_3_3: regulator-3-3v {
compatible = "regulator-fixed";
regulator-name = "v_3_3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
ap0_reg_sd_vccq: ap0_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "ap0_sd_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
states = <1800000 0x1 3300000 0x0>;
};

    cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
    compatible = "regulator-fixed";
    regulator-name = "cp0-xhci0-vbus";
    regulator-min-microvolt = ;
    regulator-max-microvolt = ;
    enable-active-high;
    };
    cp0_usb3_0_phy0: cp0_usb3_phy@0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp0_reg_usb3_vbus0>;
};

    cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
    compatible = "regulator-fixed";
    regulator-name = "cp0-xhci1-vbus";
    regulator-min-microvolt = ;
    regulator-max-microvolt = ;
    enable-active-high;
    };
    cp0_usb3_0_phy1: cp0_usb3_phy@1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp0_reg_usb3_vbus1>;
};

    cp0_reg_sd_vccq: cp0_sd_vccq@0 {
    compatible = "regulator-gpio";
    regulator-name = "cp0_sd_vccq";
    regulator-min-microvolt = ;
    regulator-max-microvolt = ;
    states = ;
    };
    cp0_reg_sd_vcc: cp0_sd_vcc@0 {
compatible = "regulator-fixed";
regulator-name = "cp0_sd_vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
};

    cp0_sfp_eth0: sfp-eth@0 {
    compatible = "sff,sfp";
    i2c-bus = <&cp0_i2c1>;
    los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
    mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
    tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
    tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
    maximum-power-milliwatt = ;
    };
    ``` keys {
    compatible = "gpio-keys";
    pinctrl-0 = <&cp0_button_pin>;
    pinctrl-names = "default";

        button0{
            /* SW3 button */
            label = "SW3";
            gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
            linux,can-disable;
            linux,code = <BTN_0>;
        };
    };
    

    };

    &uart0 {
    status = "okay";
    };

    /* on-board eMMC */
    &ap_sdhci0 {
    pinctrl-names = "default";
    bus-width = ;
    vqmmc-supply = <&ap0_reg_sd_vccq>;
    status = "okay";
    };

    &cp0_crypto {
    status = "disabled";
    };

    &cp0_ethernet {
    status = "okay";
    };

    &cp0_gpio1 {
    status = "okay";
    };

    &cp0_gpio2 {
    status = "okay";
    };

    /* EEPROM /
    &cp0_i2c0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c0_pins>;
    clock-frequency = ;
    ```
    /
    * PCA9655 GPIO expander, up to 1MHz clock.
    * 0-CON3 CLKREQ#
    * 1-CON3 PERST#
    * 2-M2 FUL_CARD_POWER_OFF
    * 3-CON3 W_DISABLE
    * 4-CON2 CLKREQ#
    * 5-USB3 overcurrent
    * 6-USB3 power
    * 7-CON2 W_DISABLE
    * 8-M2 W_DISABLE
    * 9-JP4 P4
    * 10-M2 RESET
    * 11-m.2 DEVSLP
    * 12-SFP_LOS
    * 13-SFP_TX_FAULT
    * 14-SFP_TX_DISABLE
    * 15-SFP_MOD_DEF0
    /
    expander0: gpio-expander@20 {
    /
    * This is how it should be:
    * compatible = "onnn,pca9655", "nxp,pca9555";
    * but you can't do this because of the way I2C works.
    /
    compatible = "nxp,pca9555";
    gpio-controller;
    #gpio-cells = ;
    reg = ;
    pcie1_0_clkreq {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
m2_ful_card_power_off {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2-ful-card-power-off";
};
pcie1_0_w_disable {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
usb3_power {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb3-power";
};
m2_w_disable {
gpio-hog;
gpios = <8 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-w-disable";
};
m2_reset {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2-reset";
};
m2_devslp {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
};

    / The MCP3021 supports standard and fast modes */
    mikrobus_adc: mcp3021@4c {
    compatible = "microchip,mcp3021";
    reg = ;
    };
    ``` /*EEPROM on the SOM */
    eeprom@53 {
    compatible = "atmel,24c02";
    reg = ;
    pagesize = ;
    };
    };

    /* I2C Master */
    &cp0_i2c1 {
    status = "okay";
    clock-frequency = ;
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_i2c1_pins>;
    };

    &cp0_gpio1 {
    phy_reset { /* Release switch reset */
    gpio-hog;
    gpios = ;
    output-high;
    };
    };

    &cp0_mdio {
    status = "okay";
    phy0: ethernet-phy@0 {
    /* Green led blinks on activity, Orange LED on link /
    marvell,reg-init = ;
    reg = ;
    };
    phy1: ethernet-phy@1 {
    / Green led blinks on activity, Orange LED on link */
    marvell,reg-init = ;
    reg = ;
    };
    };

    /* SRDS #0 - SATA on M.2 connector */
    &cp0_sata0 {
    status = "okay";
    };

    /* SRDS #1 - USB 3.0 host */
    &cp0_usb3_0 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy0>;
    phy-names = "usb";
    };

    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    };

    /* SRDS #2 - SFP+ 10GE */
    &cp0_eth0 {
    status = "okay";
    phy-mode = "10gbase-r";
    local-mac-address = [64 69 61 67 62 03];
    phys = <&cp0_comphy2 0>;
    managed = "in-band-status";
    sfp = <&cp0_sfp_eth0>;
    };

    /* SRDS #3 - SGMII 1GE on carrier board */
    &cp0_eth1 {
    status = "okay";
    local-mac-address = [64 69 61 67 62 01];
    phys = <&cp0_comphy3 1>;
    phy = <&phy1>;
    managed = "in-band-status";
    phy-mode = "sgmii";
    };

    /* SRDS #4 - USB 3.0 host on M.2 connector */
    &cp0_usb3_1 {
    status = "okay";
    usb-phy = <&cp0_usb3_0_phy1>;
    phy-names = "usb";
    };

    /* SRDS #5 - mini PCIe slot */
    &cp0_pcie2 {
    status = "okay";
    phys = <&cp0_comphy5 2>;
    num-lanes = ;
    reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
    };

    /* GE PHY RGMII */
    &cp0_eth2 {
    status = "okay";
    local-mac-address = [64 69 61 67 62 02];
    phy = <&phy0>;
    phy-mode = "rgmii-id";
    pinctrl-0 = <&cp0_ge2_rgmii_pins>;
    };

    &cp0_sdhci0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_sdhci_pins
    &cp0_sdhci_cd_pins>;
    bus-width = ;
    cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
    no-1-8-v;
    vqmmc-supply = <&v_3_3>;
    vmmc-supply = <&v_3_3>;
    };

    &cp0_spi1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_spi1_pins>;
    reg = ;
    spi-flash@0 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    spi-max-frequency = ;
    };
    spi-flash@1 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    /* On carrier MUX does not allow higher frequencies */
    spi-max-frequency = ;
    };
    };

    &cp0_syscon0 {
    cp0_pinctrl: pinctrl {
    compatible = "marvell,cp115-standalone-pinctrl";
    cp0_i2c0_pins: cp0-i2c-pins-0 {
    marvell,pins = "mpp37", "mpp38";
    marvell,function = "i2c0";
    };
    cp0_i2c1_pins: cp0-i2c-pins-1 {
    marvell,pins = "mpp35", "mpp36";
    marvell,function = "i2c1";
    };
    cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-0 {
    marvell,pins = "mpp44", "mpp45", "mpp46",
    "mpp47", "mpp48", "mpp49",
    "mpp50", "mpp51", "mpp52",
    "mpp53", "mpp54", "mpp55";
    marvell,function = "ge1";
    };
    cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
    marvell,pins = "mpp43";
    marvell,function = "sdio";
    };
    cp0_sdhci_pins: cp0-sdhi-pins-0 {
    marvell,pins = "mpp56", "mpp57", "mpp58",
    "mpp59", "mpp60", "mpp61";
    marvell,function = "sdio";
    };
    cp0_spi1_pins: cp0-spi-pins-1 {
    marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
    marvell,function = "spi1";
    };
    /* cp0_rcvr_clk_pins: cp0-rcvr-clk-pins {
    marvell, pins = "mpp40";
    marvell,function = "synce1";
    };*/
    cp0_button_pin: cp0-button-pin {
    marvell,pins = "mpp32";
    marvell,function = "gpio";
    };
    };
    };
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_sdhci_pins
    &cp0_sdhci_cd_pins>;
    bus-width = ;
    cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
    no-1-8-v;
    vqmmc-supply = <&v_3_3>;
    vmmc-supply = <&v_3_3>;
    };

    &cp0_spi1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cp0_spi1_pins>;
    reg = ;
    spi-flash@0 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    spi-max-frequency = ;
    };
    spi-flash@1 {
    #address-cells = ;
    #size-cells = ;
    compatible = "jedec,spi-nor";
    reg = ;
    /* On carrier MUX does not allow higher frequencies */
    spi-max-frequency = ;
    };
    };

    &cp0_syscon0 {
    cp0_pinctrl: pinctrl {
    compatible = "marvell,cp115-standalone-pinctrl";
    cp0_i2c0_pins: cp0-i2c-pins-0 {
    marvell,pins = "mpp37", "mpp38";
    marvell,function = "i2c0";
    };
    cp0_i2c1_pins: cp0-i2c-pins-1 {
    marvell,pins = "mpp35", "mpp36";
    marvell,function = "i2c1";
    };
    cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-0 {
    marvell,pins = "mpp44", "mpp45", "mpp46",
    "mpp47", "mpp48", "mpp49",
    "mpp50", "mpp51", "mpp52",
    "mpp53", "mpp54", "mpp55";
    marvell,function = "ge1";
    };
    cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
    marvell,pins = "mpp43";
    marvell,function = "sdio";
    };
    cp0_sdhci_pins: cp0-sdhi-pins-0 {
    marvell,pins = "mpp56", "mpp57", "mpp58",
    "mpp59", "mpp60", "mpp61";
    marvell,function = "sdio";
    };
    cp0_spi1_pins: cp0-spi-pins-1 {
    marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
    marvell,function = "spi1";
    };
    /* cp0_rcvr_clk_pins: cp0-rcvr-clk-pins {
    marvell, pins = "mpp40";
    marvell,function = "synce1";
    };*/
    cp0_button_pin: cp0-button-pin {
    marvell,pins = "mpp32";
    marvell,function = "gpio";
    };
    };
    };

    • [^] # Re: DTB ?

      Posté par Cyril Brulebois (site web personnel) le 22 avril 2023 à 23:28. Évalué à 2.

      

      OK pour 6.2, même si ton dmesg initial mentionnait une version 5.15…

      Tu pourrais préciser où sont les patches constructeur ? Est-ce que les datasheets (avec le pinning/routage interne) sont disponibles ? Note : Je me trompe peut-être lourdement sur cette histoire d'eth1/eth2, mais qui n'a jamais fait une erreur (copier-coller ou autre) dans un fichier DTS…

      Debian Consultant @ DEBAMAX

      • [^] # Re: DTB ?

        Posté par doudootiana le 22 avril 2023 à 23:33. Évalué à 1.

        

        RE :)

        Tu as raison, le dmesg que j'ai mis était avec la version kernel 5.15.
        J'ai testé avec la 5.15 et la 6.2.
        Mais ayant le même résultat, je préfère conserver la version 6.2

        Les patches se trouvent ici : Texte du lien

        Et ici tu as le datasheets et block diagram : Texte du lien

        Merci encore pour ton aide.

        • [^] # Re: DTB ?

          Posté par doudootiana le 22 avril 2023 à 23:55. Évalué à 1.

          

          Ici le log quand j'active les interfaces eth1 et eth2 :
          ```
          ifup eth1
          [ 108.988416] mvpp2 f2000000.ethernet eth1: PHY [f212a200.mdio-mii:01] driver Marvell 88E1510
          [ 108.999168] mvpp2 f2000000.ethernet eth1: configuring for inband/sgmii link mode
          udhcpc: started, v1.35.0
          udhcpc: broadcasting discover
          [ 112.059960] mvpp2 f2000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
          [ 112.068004] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
          udhcpc: broadcasting discover
          udhcpc: broadcasting select for 192.168.4.63, server 192.168.4.254
          udhcpc: lease of 192.168.4.63 obtained from 192.168.4.254, lease time 86400
          deleting routers
          adding dns 192.168.4.254

          ifup eth2

          [ 73.348678] mvpp2 f2000000.ethernet eth2: PHY [f212a200.mdio-mii:00] driver Marvell 88E1510
          [ 73.358352] mvpp2 f2000000.ethernet eth2: configuring for phy/rgmii-id link mode
          udhcpc: started, v1.35.0
          udhcpc: broadcasting discover
          [ 76.444184] mvpp2 f2000000.ethernet eth2: Link is Up - 1Gbps/Full - flow control rx/tx
          [ 76.452227] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
          udhcpc: broadcasting discover
          udhcpc: broadcasting discover
          udhcpc: no lease, forking to background
          ```

        • [^] # Re: DTB ?

          Posté par Cyril Brulebois (site web personnel) le 23 avril 2023 à 01:54. Évalué à 3.

          

          Alors les « patches » n'aident malheureusement pas du tout, puisqu'il y a 3 fichiers, et ça ne dit pas lequel est utilisé dans ton cas.

          Les datasheets/block diagrams ne donnent aucune information technique… :(

          Au mieux, en farfouillant dans HW info on a un lien vers Atlassian qui ensuite pointe vers une image, dans laquelle on trouve un /boot/cn9130-cf-base.dtb (qui peut être examinée via dtc). Est-ce cela que tu utilises ?

          Quoi qu'il en soit, il semble s'agir d'un adaptateur Ethernet double, du coup je continue à ne pas comprendre pourquoi les deux ports ont des modes différents. J'ai réussi à trouver le pinout du Marvell 88E1512 qui semble être embarqué, mais pas la façon dont il est utilisé dans ton produit…

          Si je regarde la DTB susmentionnée, on a ceci (je condense à nouveau) :

          ethernet@0 {
            eth0 {
              phys = <0x1c 0x00>;
              managed = "in-band-status";
            };
          
            eth1 {
              phys = <0x1e 0x01>;
              phy = <0x1f>;
              managed = "in-band-status";
              phy-mode = "sgmii";
            };
          
            eth2 {
              phy = <0x20>;
              phy-mode = "rgmii-id";
              pinctrl-0 = <0x21>;
            };
          }
          
          mdio@12a200 {
            ethernet-phy@0 {
              phandle = <0x20>;
            };
          
            ethernet-phy@1 {
              phandle = <0x1f>;
            };
          };
          
          pinctrl {
            cp0-ge-rgmii-pins-0 {
              marvell,pins = "mpp44\0mpp45\0mpp46\0mpp47\0mpp48\0mpp49\0mpp50\0mpp51\0mpp52\0mpp53\0mpp54\0mpp55";
              marvell,function = "ge1";
              phandle = <0x21>;
            };
          };
          

          Ce qui ne descend pas mon niveau de perplexité :

          • on garde en tête que phandle c'est grossièrement une notion de référence ;
          • dans mdio@12a200, les deux sections ethernet-phy@0 et ethernet-phy@1 semblent bien correspondre aux interfaces eth2 et eth1 respectivement (le genre de symétrie que j'attendais) ;
          • pourtant l'interface eth2 a un mode différent ;
          • et l'interface eth2 passe par un pinctrl plutôt que d'avoir un attribut phys directement.

          C'est là que les docs précises d'architecture pourraient permettre de vérifier que tout est branché et déclaré correctement.

          Cela étant, je n'y connais rien en matériel, donc une fois ces observations random effectuées, je t'invite à contacter le support pour vérifier si l'interface est effectivement censée fonctionner, et s'il y a une configuration particulière pour celle-ci.

          Et pour clore ma probable dernière intervention sur ce fil vu que je suis au bout de ma besace : ça me rappelle les histoires de RTC sur le CM4, de routage configurable de certains pins/gpios, pour lesquels il était question d'utiliser du pin muxing (e.g. i2c-mux-pinctrl). Pour que cela fonctionne il fallait activer certaines options de noyau (e.g. CONFIG_I2C_MUX_PINCTRL). Il pourrait être pertinent d'activer tout ce qui ressemble à du PINCTRL, juste pour être sûr que ça n'est pas un module qui serait trivialement manquant. Ceci dit, je n'ai aucune idée de si on s'attend à avoir une interface qui apparaît et qui arrive à Link is Up si c'est une partie du problème…

          Au passage, je note de fuir SolidRun, qui n'a pas fait intégrer ses DTB dans mainline. Ça me rappelle une certaine fondation couleur framboise…

          Debian Consultant @ DEBAMAX

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